page 1 qw -bp018 rev :f comchip t echnology co., l td. CSRS065V0P mechanical data -case: standard package, sot -23-6 molded plastic. -t erminals: solder plated, solderable per mil-std-750,method 2026. -mounting position: any -w eight: 0.015 gram (approx.). 1 3 4 6 2 5 pin configuration circuit diagram c 260 ( 10 sec) t sol lead soldering temperature c -55 to +85 t j operating temperature a 6.5 i pp peak pulse current ( tp = 8/20 us) parameter symbol v alue unit 6 5 4 1 2 3 kv esd _vdd esd per iec 61000-4-2(air)(vdd-gnd) esd per iec 61000-4-2(contact)(vdd-gnd) 30 kv 18 esd esd per iec 61000-4-2(air) esd per iec 61000-4-2(contact) 14 -55 to +125 storage temperature t stg c dc voltage at any i/o pin v io (gnd -0.5) to (vdd +0.5) v low capacitance esd protection array rohs device maximum ratings (at t a=25c unless otherwise noted) d i m e n s i o n s i n i n c h e s a n d ( m i l l i m e t e r ) s o t - 2 3 - 6 0.1 19(3.02) 0.1 1 1(2.82) 0.067(1.70) 0.059(1.50) 0.079(2.00) 0.071(1.80) 0.045(1.15) 0.041(1.05) 0.020(0.50) 0.012(0.30) 0.004(0.10) 0.024(0.60) 0.1 16(2.95) 0.104(2.65) 0.008(0.20) 0.004(0.10) 0.012(0.30) 0.000(0.00) company reserves the right to improve product design , functions and reliability without notice. features -esd protect for 4 high-speed i/o channels. -iec61000-4-2 level 4 esd protection. -iec61000-4-4 (fet)20a for i/o,80a for power . -w orking voltage: 5v -low capacitance:1.3pf(t yp.). -high component density . 0.037(0.95) bsc.
page 2 rev :f comchip t echnology co., l td. v 5 v r wm reverse leakage current reverse stand-off voltage parameter conditions symbol min t yp ma x unit v r wm = 5 v , pin 5 to pin 2 pin 5 to pin 2 v pin 5 = 5 v , v pin 2 =0v ,v io = 0~5v i r diode breakdown voltage i r = 1 ma, pin 5 to pin 2 ua v bd forward voltage i f = 15 ma, pin 2 to pin 5 v f v 1 clamping voltage i pp = 5 a, tp=8/20us, any channel pin to ground v c v iec 61000-4-2 +6kv ,contact mode any channel pin to ground iec 61000-4-2 +6kv ,contact moed vdd pin to ground 9 9 12.5 8.1 0.8 6 junction capacitance v pin5 = 5v ,v pin2 = 0v , v io =2.5v , f = 1mhz,any channel pin to ground c j 1.3 pf 1.6 v pin5 = 5v ,v pin2 = 0v , v io =2.5v f = 1mhz,between channel pins 0.12 0.14 v pin5 = 5v ,v pin2 = 0v , v in =2.5v f = 1mhz,channel_x pin to ground - channel_y pin to ground 0.05 0.07 5 9 1 v qw -bp018 low capacitance esd protection array electrical characteristics (at t a=25c unless otherwise noted) company reserves the right to improve product design , functions and reliability without notice.
page 3 rev :f comchip t echnology co., l td. ra ting and characteristic cur ves (CSRS065V0P) % o f r a t e d p o w e r o r i p p 0 ambient temperature (c) fig. 1 - power derating curve c l a m p i n g v o l t a g e ( v ) peak pulse current (a) 0 4 . 5 fig. 2 - clamping voltage vs. peak pulse current f o r w a r d v o l t a g e ( v ) peak pulse current(a) fig.3 - forward voltage v .s. forward current input voltage (v) i n p u t c a p a c i t a n c e ( p f ) fig.4 - t ypical variation of c in v .s. v in 0 1 0 0 5 0 2 5 1 2 5 7 5 1 5 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 w aveform parameters: tr=8us td=20us i/o pin to gnd pin 5 . 0 5 . 5 6 . 0 6 . 5 7 . 0 7 . 5 1 1 1 1 2 1 0 9 8 7 6 5 4 3 2 0 4 . 5 w aveform parameters: tr=8us td=20us i/o pin to gnd pin 5 . 0 5 . 5 6 . 0 6 . 5 7 . 0 7 . 5 4 . 0 3 . 5 3 . 0 2 . 5 2 . 0 1 . 5 1 . 0 0 . 5 vdd =5v ,gnd =0v ,f =1mhz,t a =25c 0 5 4 3 2 1 0 . 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 1 . 2 1 . 4 1 . 6 1 . 8 2 . 0 i n p u t c a p a c i t a n c e ( p f ) 2 0 t emperature (c) fig. 5 - t ypical variation of c in v .s. temperature 0 fig. 6 - t ransmission line pulsing (tlp) measurement 1 . 0 0 8 0 4 0 1 0 0 6 0 1 2 0 1 . 0 5 1 . 1 0 1 . 1 5 1 . 2 0 1 . 2 5 1 . 3 0 1 . 3 5 1 . 4 0 1 . 4 5 1 . 5 0 vdd =5v ,gnd =0v ,v in =2.5v f=1mhz t r a n s m i s s i o n l i n e p u l s i n g ( t l p ) c u r r e n t ( a ) t ransmission line pulsing(tlp)voltage(v) 0 1 3 5 6 2 4 7 8 1 8 1 4 1 2 1 0 8 6 4 2 1 6 v _ p u l s e 1 0 0 n s p u l s e f r o m a t r a n s m i s s i o n l i n e d u t + t l p _ v t l p _ i i/o to gnd t r a n s m i s s i o n l i n e p u l s i n g ( t l p ) c u r r e n t ( a ) t ransmission line pulsing(tlp)voltage(v) fig.7 -t ransmission line pulsing (tlp) measurement 0 0 1 3 5 6 9 1 0 1 8 1 4 1 2 1 0 8 6 4 2 1 6 + - 1 0 0 n s t l p _ i v _ p u l s e p u l s e f r o m a t r a n s m i s s i o n l i n e d u t t l p _ v 2 4 7 8 vdd to gnd qw -bp018 low capacitance esd protection array company reserves the right to improve product design , functions and reliability without notice.
page 4 rev :f comchip t echnology co., l td. qw -bp018 reel t aping specification low capacitance esd protection array company reserves the right to improve product design , functions and reliability without notice. d f e b p 1 p 0 o 1 2 0 d 1 d 2 w 1 p d a w t c b c d d d 2 d 1 s o t - 2 3 - 6 s y m b o l ( m m ) ( i n c h ) 2 . 3 6 2 0 . 0 2 0 4 . 0 0 0 . 1 0 1 . 5 0 0 . 0 5 6 0 . 0 0 0 . 5 0 1 3 . 0 0 0 . 2 0 4 . 0 0 0 . 1 0 2 . 0 0 0 . 0 5 0 . 0 5 9 0 . 0 0 2 0 . 5 1 2 0 . 0 0 8 s y m b o l ( m m ) ( i n c h ) 0 . 1 5 7 0 . 0 0 4 0 . 1 5 7 0 . 0 0 4 0 . 0 7 9 0 . 0 0 2 e f p p 0 p 1 w w 1 1 . 7 5 0 . 1 0 0 . 0 6 9 0 . 0 0 4 3 . 5 0 0 . 0 5 0 . 1 3 8 0 . 0 0 2 s o t - 2 3 - 6 3 . 1 7 0 . 1 0 0 . 1 2 5 0 . 0 0 4 3 . 2 3 0 . 1 0 0 . 1 2 7 0 . 0 0 4 1 . 3 7 0 . 1 0 0 . 0 5 4 0 . 0 0 4 1 2 . 3 0 0 . 2 0 0 . 4 8 4 0 . 0 0 8 8 . 0 0 + 0 . 3 0 / C 0 . 1 0 0 . 3 1 5 + 0 . 0 1 2 / C 0 . 0 0 4 a 1 8 0 . 0 + 0 . 0 0 / C 0 . 3 0 7 . 0 8 7 + 0 . 0 0 / C 0 . 0 1 2
page 5 rev :f comchip t echnology co., l td. qw -bp018 marking code c05 1 2 3 6 4 part number CSRS065V0P marking code c05 5 low capacitance esd protection array company reserves the right to improve product design , functions and reliability without notice. size (inch) 0.043 (mm) 1.10 0.60 0.95 0.024 0.037 2.50 0.098 e 3.60 0.142 b c d a sot -23-6 suggested p ad layout a d c b e s o - 2 3 - 6 t standard packaging c a s e t y p e 3 , 0 0 0 r e e l ( p c s ) reel size (inch) 7 r e e l p a c k
|
